1. Field of the Invention
The present invention relates generally to semiconductor structures, and more particularly to semiconductor-on-insulator structures and methods for making semiconductor-on-insulator structures.
To date, the semiconductor material most commonly used in semiconductor-on-insulator structures has been silicon. Such structures have been referred to in the literature as silicon-on-insulator structures and the abbreviation “SOI” has been applied to such structures. The present invention relates to semiconductor-on-insulator structures in general, including silicon-on-insulator structures.
For ease of presentation, the following discussion will at times be in terms of silicon-on-insulator structures. The references to this particular type of semiconductor-on-insulator structure are made to facilitate the explanation of the invention and are not intended to, and should not be interpreted as, limiting the invention's scope in any way.
The SOI abbreviation is used herein to refer to semiconductor-on-insulator structures in general, including, but not limited to, silicon-on-insulator structures. Similarly, the SOG abbreviation is used to refer to semiconductor-on-glass structures in general, including, but not limited to, silicon-on-glass structures. The SOG nomenclature is also intended to include semiconductor-on-glass-ceramic structures, including, but not limited to, silicon-on-glass-ceramic structures. The abbreviation SOI encompasses SOGs.
2. Technical Background
Silicon-on-insulator technology is becoming increasingly important for high performance thin film transistors, solar cells, and displays, such as, active matrix displays. The silicon-on-insulator wafers consist of a thin layer of substantially single crystal silicon (generally 0.1-0.3 microns in thickness but, in some cases, as thick as 5 microns) on an insulating material.
Various ways of obtaining such a wafer include epitaxial growth of Si on lattice matched substrates; bonding of a single crystal silicon wafer to another silicon wafer on which an oxide layer of SiO2 has been grown, followed by polishing or etching of the top wafer down to, for example, a 0.1 to 0.3 micron layer of single crystal silicon; or ion-implantation methods in which either hydrogen or oxygen ions are implanted either to form a buried oxide layer in the silicon wafer topped by Si in the case of oxygen ion implantation or to separate (exfoliate) a thin Si layer to bond to another Si wafer with an oxide layer as in the case of hydrogen ion implantation. Of these three approaches, the approaches based on ion implantation have been found to be more practical commercially. In particular, the hydrogen ion implantation method has an advantage over the oxygen implantation process in that the implantation energies required are less than 50% of that of oxygen ion implants and the dosage required is two orders of magnitude lower.
Exfoliation by the hydrogen ion implantation method was initially taught in, for example, Bister et al., “Ranges of the 0.3-2 MeV H+ and 0.7-2 MeV H2+ Ions in Si and Ge,” Radiation Effects, 1982, 59:199-202, and has been further demonstrated by Michel Bruel. See Bruel, U.S. Pat. No. 5,374,564; M. Bruel, Electronic Lett. 31, 1995 pp 1201-1202; and L. Dicioccio, Y. Letiec, F. Letertre, C. Jaussad and M. Bruel, Electronic Lett. 32, 1996, pp 1144-1145. Each of the above-referenced publications are hereby incorporated herein by reference. The method typically consists of the following steps. A thermal oxide layer is grown on a single crystal silicon wafer. Hydrogen ions are then implanted into this wafer to generate subsurface flaws. The implantation energy determines the depth at which the flaws are generated and the dosage determines flaw density. This wafer is then placed into contact with another silicon wafer (the support substrate) at room temperature to form a tentative bond. The wafers are then heat-treated to about 600° C. to cause growth of the subsurface flaws for use in separating a thin layer of silicon from the Si wafer. The resulting assembly is then heated to a temperature above 1,000° C. to fully bond the Si film with SiO2 underlayer to the support substrate, i.e., the unimplanted Si wafer. This process thus forms a silicon-on-insulator structure with a thin film of silicon bonded to another silicon wafer with an oxide insulator layer in between.
Cost is an important consideration for commercial applications of SOI structures. To date, a major part of the cost of such structures has been the cost of the silicon wafer which supports the oxide layer, topped by the Si thin film, i.e., a major part of the cost has been the support substrate. Although the use of quartz as a support substrate has been mentioned in various patents (see U.S. Pat. Nos. 6,140,209; 6,211,041; 6,309,950; 6,323,108; 6,335,231; and 6,391,740), quartz is itself a relatively expensive material. In discussing support substrates, some of the above references have mentioned quartz glass, glass, and glass-ceramics. Other support substrate materials listed in these references include diamond, sapphire, silicon carbide, silicon nitride, ceramics, metals, and plastics.
As the present inventors discovered, it is not at all a simple matter to replace a silicon wafer with a wafer made out of a less expensive material in an SOI structure. In particular, it is difficult to replace a silicon wafer with a glass or glass-ceramic of the type which can be manufactured in large quantities at low cost, i.e., it is difficult to make cost effective SOG structures. This is so because prior to the present invention, the art has not had practical techniques for using glass or glass-ceramics as support substrates in semiconductor-on-insulator structures.
The “strained silicon effect” has been used to obtain higher electron mobilities and hole mobilities in silicon-based semiconductor materials. As described in U.S. Pat. Nos. 6,107,653 and 6,539,641, strained silicon films have been grown by depositing SiGe layers of gradually increasing Ge concentration onto a silicon wafer, then a silicon layer is formed on the topmost SiGe layer. The thermal expansion mismatch between the SiGe layer and the silicon layer puts the silicon layer under tensile stress. In the strained silicon layer, electrons experience less resistance and flow up to 70 percent faster than in unstrained silicon, leading to microelectronics devices that are up to 35% faster than comparably-sized devices made in unstrained silicon. However, the cost of strained silicon substrates can be high, because prior to the present invention, the art has not had practical techniques for making semiconductor-on-insulator structures having a strained semiconductor layer and glass or glass-ceramics as the support substrate.